\begin{multicols}{2}
[
\section{AND}
]

\subsection{VHDL}
 \begin{minted}{vhdl}
/**
 * And gate: 
 * out = 1 if (a == 1 and b == 1)
 *       0 otherwise
 */

CHIP And {
    IN a, b;
    OUT out;

    PARTS:
        Nand(a=a ,b=b ,out=nandout);
        Not(in=nandout ,out=out);
}
\end{minted}

\subsection{Wertetabelle}
\begin{table}[H]
    \centering
    \begin{tabular}{cc|c}
         a&  b& a $\wedge$ b\\ \hline
         0&  0& 0\\
         0&  1& 0\\
         1&  0& 0\\
         1&  1& 1\\
    \end{tabular}
    \label{tab:and}
\end{table}

\subsection{Aufbau mit Nand}
\begin{figure}[H]
\centering
    \centering
    \input{Grafiken/AndANSI}
    \caption{Enter Caption}
    \label{fig:enter-label}
\end{figure}


\subsection{Darstellung nach IEC}
\begin{figure}[H]
\centering
    \centering
    \includegraphics[width=0.75\linewidth]{IEC/AndIEC.png}
    \caption{Enter Caption}
    \label{fig:enter-label}
\end{figure}


\end{multicols}



