\begin{multicols*}{2}
[
\section{OR}
]

\subsection{VHDL}
\begin{minted}{vhdl}
 /**
 * Or gate:
 * out = 1 if (a == 1 or b == 1)
 *       0 otherwise
 */

CHIP Or {
    IN a, b;
    OUT out;

    PARTS:
    Not(in=a,out=nota);
    Not(in=b,out=notb);
    Nand(a=nota,b=notb,out=out);
}
\end{minted}

\subsection{Wertetabelle}
\begin{table}[H]
    \centering
    \begin{tabular}{cc|c}
         a&  b& out\\ \hline
         0&  0& 0\\
         0&  1& 1\\
         1&  0& 1\\
         1&  1& 1\\
    \end{tabular}
    \label{tab:or}
\end{table}

\subsection{Aufbau mit Nand}
\begin{figure}[H]
\centering
    \centering
    \include{Grafiken/OrANSIComplete}
    \caption{Enter Caption}
    \label{fig:enter-label}
\end{figure}

\subsection{Darstellung nach ANSI}
\begin{figure}[H]
\centering
    \centering
    \include{Grafiken/OrANSI}
    \caption{Enter Caption}
    \label{fig:enter-label}
\end{figure}

\subsection{Darstellung nach IEC}
\begin{figure}[H]
\centering
    \centering
    \includegraphics[width=0.75\linewidth]{IEC/OrIEC.png}
    \caption{Enter Caption}
    \label{fig:enter-label}
\end{figure}


\end{multicols*}

