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Das erste richtige Bild mit circuittikz

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Sven Riwoldt
2023-05-01 19:13:45 +02:00
parent 1fb8d9e7aa
commit 06ce790e33
18 changed files with 1514 additions and 0 deletions
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Nand2tetris_prj/001_Not.dat Normal file
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Nand2tetris_prj/001_Not.dpl Normal file
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<QucsStudio Schematic 4.3.1>
<Properties>
View=0,0,800,800,1,0,0
Grid=10,10,0
DataSet=*.dat
DataDisplay=*.sch
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showFrame=0
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FrameText2=Datum:
FrameText3=Revision:
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<Truth 100 110 80 80 71 #c0c0c0 1 00 1 0 1 1 1 0 1 1 1 0 1 1 315 0 225 "" "" "">
<"out.X" "" #0000ff 0 3 0 0 0 0 "">
</Truth>
</Diagrams>
<Paintings>
</Paintings>

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Nand2tetris_prj/001_Not.sch Normal file
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<QucsStudio Schematic 4.3.1>
<Properties>
View=0,-18,800,800,1,0,0
Grid=10,10,1
DataSet=*.dat
DataDisplay=*.dpl
OpenDisplay=1
showFrame=0
FrameText0=Titel
FrameText1=Gezeichnet von:
FrameText2=Datum:
FrameText3=Revision:
</Properties>
<Symbol>
</Symbol>
<Components>
DigiSource S1 1 110 70 -35 16 0 0 "1" 1 "low" 0 "1ns; 1ns" 0 "1 V" 0
NAND Y1 1 190 70 -26 27 0 0 "2" 0 "1 V" 0 "0" 0 "old" 0
.Digi Digi1 1 100 150 0 63 0 0 "TruthTable" 0 "1ns" 0 "VHDL" 1
VHDL X1 1 320 170 -26 21 0 0 "001_Not.vhdl" 1
</Components>
<Wires>
160 60 160 70 "" 0 0 0 ""
160 70 160 80 "" 0 0 0 ""
110 70 160 70 "" 0 0 0 ""
220 70 220 70 "out" 250 20 0 ""
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<Diagrams>
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<Paintings>
</Paintings>

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Nand2tetris_prj/001_Not.vhdl Normal file
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library ieee;
use ieee.std_logic_1164.all;
entity notGate is
port (a, b : in std_logic;
out : out std_logic);
end notGate;
architecture hardware of notGate is
begin
out <= a nand a;
end hardware;

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Nand2tetris_prj/002_And.dat Normal file
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Nand2tetris_prj/002_And.dpl Normal file
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<QucsStudio Schematic 4.3.1>
<Properties>
View=0,0,800,800,1,0,0
Grid=10,10,0
DataSet=*.dat
DataDisplay=*.sch
OpenDisplay=1
showFrame=0
FrameText0=Titel
FrameText1=Gezeichnet von:
FrameText2=Datum:
FrameText3=Revision:
</Properties>
<Symbol>
</Symbol>
<Components>
</Components>
<Wires>
</Wires>
<Diagrams>
<Truth 100 250 360 220 71 #c0c0c0 1 00 1 0 1 1 1 0 1 1 1 0 1 1 315 0 225 "" "" "">
<"out.X" "" #0000ff 0 3 0 0 0 0 "">
</Truth>
</Diagrams>
<Paintings>
</Paintings>

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Nand2tetris_prj/002_And.sch Normal file
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<QucsStudio Schematic 4.3.1>
<Properties>
View=0,0,800,800,1,0,0
Grid=10,10,1
DataSet=*.dat
DataDisplay=*.dpl
OpenDisplay=1
showFrame=0
FrameText0=Titel
FrameText1=Gezeichnet von:
FrameText2=Datum:
FrameText3=Revision:
</Properties>
<Symbol>
</Symbol>
<Components>
DigiSource S1 1 120 90 -35 16 0 0 "1" 1 "low" 0 "1ns; 1ns" 0 "1 V" 0
NAND Y1 1 200 90 -26 27 0 0 "2" 0 "1 V" 0 "0" 0 "old" 0
.Digi Nand 1 110 170 0 63 0 0 "TruthTable" 0 "10 ns" 0 "VHDL" 1
</Components>
<Wires>
170 80 170 90 "" 0 0 0 ""
170 90 170 100 "" 0 0 0 ""
120 90 170 90 "" 0 0 0 ""
230 90 230 90 "out" 260 40 0 ""
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<Diagrams>
</Diagrams>
<Paintings>
</Paintings>

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Nand2tetris_prj/And.vhdl Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND_GATE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
O : out STD_LOGIC);
end NAND_GATE;
entity and_nor_top is
Port ( IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC;
IN3 : in STD_LOGIC;
IN4 : in STD_LOGIC;
OUT1 : out STD_LOGIC;
OUT2 : out STD_LOGIC);
end nand_nor_top;
architecture Behavioral of nand_nor_top is
signal A1 : STD_LOGIC;
signal A2 : STD_LOGIC;
signal X1 : STD_LOGIC;
signal B1 : STD_LOGIC;
signal B2 : STD_LOGIC;
signal Y1 : STD_LOGIC;
begin
X1 <= A1 nand A2;
Y1 <= B1 nor B2;
-- compensation for inverting inputs and outputs
A1 <= not IN1;
A2 <= not IN2;
OUT1 <= not X1;
B1 <= not IN3;
B2 <= not IN4;
OUT2 <= not Y1;
end Behavioral;

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Nand2tetris_prj/Nand.vhdl Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity NAND_GATE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
O : out STD_LOGIC);
end NAND_GATE;
architecture Behavioral of NAND_GATE is
begin
O <= not (A and B);
end Behavioral;