Das erste richtige Bild mit circuittikz

This commit is contained in:
Sven Riwoldt
2023-05-01 19:13:45 +02:00
parent 1fb8d9e7aa
commit 06ce790e33
18 changed files with 1514 additions and 0 deletions

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library ieee;
use ieee.std_logic_1164.all;
entity notGate is
port (a, b : in std_logic;
out : out std_logic);
end notGate;
architecture hardware of notGate is
begin
out <= a nand a;
end hardware;