From 3ad3d596b0a6e45761d1f077481c1c394c18a7e0 Mon Sep 17 00:00:00 2001 From: Sven Riwoldt Date: Sun, 6 Aug 2023 10:44:10 +0200 Subject: [PATCH] Projekt 5 beendet, ein Krampf --- projects/05/CPU.hdl | 107 ++++++++++++++++++++++++--------------- projects/05/Computer.hdl | 4 +- projects/05/Memory.hdl | 7 ++- 3 files changed, 74 insertions(+), 44 deletions(-) diff --git a/projects/05/CPU.hdl b/projects/05/CPU.hdl index dfd8a63..1767a95 100644 --- a/projects/05/CPU.hdl +++ b/projects/05/CPU.hdl @@ -1,30 +1,30 @@ -// This file is part of www.nand2tetris.org -// and the book "The Elements of Computing Systems" -// by Nisan and Schocken, MIT Press. -// File name: projects/05/CPU.hdl - -/** - * The Hack CPU (Central Processing unit), consisting of an ALU, - * two registers named A and D, and a program counter named PC. - * The CPU is designed to fetch and execute instructions written in - * the Hack machine language. In particular, functions as follows: - * Executes the inputted instruction according to the Hack machine - * language specification. The D and A in the language specification - * refer to CPU-resident registers, while M refers to the external - * memory location addressed by A, i.e. to Memory[A]. The inM input - * holds the value of this location. If the current instruction needs - * to write a value to M, the value is placed in outM, the address - * of the target location is placed in the addressM output, and the - * writeM control bit is asserted. (When writeM==0, any value may - * appear in outM). The outM and writeM outputs are combinational: - * they are affected instantaneously by the execution of the current - * instruction. The addressM and pc outputs are clocked: although they - * are affected by the execution of the current instruction, they commit - * to their new values only in the next time step. If reset==1 then the - * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather - * than to the address resulting from executing the current instruction. - */ - +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/05/CPU.hdl + +/** + * The Hack CPU (Central Processing unit), consisting of an ALU, + * two registers named A and D, and a program counter named PC. + * The CPU is designed to fetch and execute instructions written in + * the Hack machine language. In particular, functions as follows: + * Executes the inputted instruction according to the Hack machine + * language specification. The D and A in the language specification + * refer to CPU-resident registers, while M refers to the external + * memory location addressed by A, i.e. to Memory[A]. The inM input + * holds the value of this location. If the current instruction needs + * to write a value to M, the value is placed in outM, the address + * of the target location is placed in the addressM output, and the + * writeM control bit is asserted. (When writeM==0, any value may + * appear in outM). The outM and writeM outputs are combinational: + * they are affected instantaneously by the execution of the current + * instruction. The addressM and pc outputs are clocked: although they + * are affected by the execution of the current instruction, they commit + * to their new values only in the next time step. If reset==1 then the + * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather + * than to the address resulting from executing the current instruction. + */ + CHIP CPU { IN inM[16], // M value input (M = contents of RAM[A]) @@ -45,21 +45,44 @@ CHIP CPU { //Controlbus // A/C-Instruction and Controlbus Not(in=instruction[15],out=on); - OR(a=on,b=instruction[5],out=); - AND(a=instruction[15],b=instruction[12],out=); - AND(a=instruction[15],b=instruction[4],out=); - AND(a=instruction[15],b=instruction[3],out=); - AND(a=instruction[15],b=instruction[0],out=); - AND(a=instruction[15],b=instruction[1],out=); - AND(a=instruction[15],b=instruction[2],out=); + //d1 + Or(a=on,b=instruction[5],out=loadA); + And(a=instruction[15],b=instruction[12],out=AoderMem); + //d2 + And(a=instruction[15],b=instruction[4],out=loadD); + //d3 -- writeM + And(a=instruction[15],b=instruction[3],out=writeM); + //j3 + And(a=instruction[15],b=instruction[0],out=j3); + //j2 + And(a=instruction[15],b=instruction[1],out=j2); + //j1 + And(a=instruction[15],b=instruction[2],out=j1); Not(in=zr,out=notzr); Not(in=ng,out=notng); - AND(a=notzr,b=notng,out=); - AND(a=,b=,out=); - AND(a=,b=,out=); - AND(a=,b=,out=); - OR(a=,b=,out=); - OR(a=,b=,out=); + And(a=notzr,b=notng,out=notzrAndNoting); + And(a=notzrAndNoting,b=j3,out=jg3); - Mux16(a=outM,b=instruction,sel=on,out=) -} \ No newline at end of file + And(a=zr,b=j2,out=jg2); + And(a=ng,b=j1,out=jg1); + Or(a=jg3,b=jg2,out=jg23); + Or(a=jg23,b=jg1,out=loadPC); + + // Hier addressM[15]-Ausgang der CPU + ARegister(in=mux1,load=loadA,out=outAReg,out[0..14]=addressM); + + //M1 + Mux16(a=outM2,b=instruction,sel=on,out=mux1); + //M2 + Mux16(a=outAReg,b=inM,sel=AoderMem,out=AM); + + DRegister(in=outM2,load=loadD,out=outD); + + // Das out könnte nicht funktionieren, d.h. die Verteilung zum D-Register und zum Mux + + ALU(x=outD,y=AM,zx=instruction[11],nx=instruction[10],zy=instruction[9],ny=instruction[8],f=instruction[7],no=instruction[6],zr=zr,ng=ng,out=outM,out=outM2); + + //Counter + PC(in=outAReg,load=loadPC, inc=true,reset=reset,out[0..14]=pc); + + } \ No newline at end of file diff --git a/projects/05/Computer.hdl b/projects/05/Computer.hdl index 22f9b48..d577d2b 100644 --- a/projects/05/Computer.hdl +++ b/projects/05/Computer.hdl @@ -19,5 +19,7 @@ CHIP Computer { IN reset; PARTS: - // Put your code here: + CPU(inM=inmm, instruction=ins, reset=reset, outM=outtm, writeM=wm, addressM=am, pc=pco); + Memory(in=outtm, load=wm, address=am, out=inmm); + ROM32K(address=pco, out=ins); } diff --git a/projects/05/Memory.hdl b/projects/05/Memory.hdl index 62a4fd2..954656b 100644 --- a/projects/05/Memory.hdl +++ b/projects/05/Memory.hdl @@ -27,5 +27,10 @@ CHIP Memory { OUT out[16]; PARTS: - // Put your code here: + DMux4Way(in=load,sel=address[13..14],a=ram1,b=ram2,c=loadscreen,d=loadkeyboard); + Or(a=ram1, b=ram2, out=ramload); + RAM16K(in=in, load=ramload, address=address[0..13], out=outram); + Screen(in=in, load=loadscreen, address=address[0..12], out=outscreen); + Keyboard(out=outkeyb); + Mux4Way16(a=outram, b=outram, c=outscreen, d=outkeyb, sel=address[13..14], out=out); } \ No newline at end of file