Init nand2tetris

projects/03/einreichung/Bit.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/a/Bit.hdl
+
+/**
+ * 1-bit register:
+ * If load[t] == 1 then out[t+1] = in[t]
+ *                 else out does not change (out[t+1] = out[t])
+ */
+
+CHIP Bit {
+    IN in, load;
+    OUT out;
+
+    PARTS:
+    Mux(a=outdff, b=in, sel=load, out=outmux);
+    DFF(in=outmux, out=out, out=outdff);
+}

projects/03/einreichung/PC.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/a/PC.hdl
+
+/**
+ * A 16-bit counter with load and reset control bits.
+ * if      (reset[t] == 1) out[t+1] = 0
+ * else if (load[t] == 1)  out[t+1] = in[t]
+ * else if (inc[t] == 1)   out[t+1] = out[t] + 1  (integer addition)
+ * else                    out[t+1] = out[t]
+ */
+
+CHIP PC {
+    IN in[16],load,inc,reset;
+    OUT out[16];
+
+
+    PARTS:
+
+    //Inc, Rückkopplung des out und +1
+    Inc16(in=toinc, out=outinc);
+
+    //inc-flag
+    Mux16(a=outtomux, b=outinc, sel=inc, out=outmuxinc);
+    //load-flag, wenn 1 dann schiebe in auf das in des Registers
+    Mux16(a=outmuxinc, b=in, sel=load, out=outmuxload);
+    //reset-flag
+    Mux16(a=outmuxload, b=false, sel=reset, out=outmuxreset);
+    //Register
+    Register(in=outmuxreset, load=true, out=out, out=toinc, out=outtomux);
+}

projects/03/einreichung/RAM16K.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/b/RAM16K.hdl
+
+/**
+ * Memory of 16K registers, each 16 bit-wide. Out holds the value
+ * stored at the memory location specified by address. If load==1, then 
+ * the in value is loaded into the memory location specified by address 
+ * (the loaded value will be emitted to out from the next time step onward).
+ */
+
+CHIP RAM16K {
+    IN in[16], load, address[14];
+    OUT out[16];
+
+    PARTS:
+    DMux4Way(in=load, sel=address[0..1], a=load1, b=load2, c=load3, d=load4);
+    RAM4K(in=in, load=load1, address=address[2..13], out=outram1);
+    RAM4K(in=in, load=load2, address=address[2..13], out=outram2);
+    RAM4K(in=in, load=load3, address=address[2..13], out=outram3);
+    RAM4K(in=in, load=load4, address=address[2..13], out=outram4);
+    Mux4Way16(a=outram1, b=outram2, c=outram3, d=outram4,sel=address[0..1], out=out);
+}

projects/03/einreichung/RAM4K.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/b/RAM4K.hdl
+
+/**
+ * Memory of 4K registers, each 16 bit-wide. Out holds the value
+ * stored at the memory location specified by address. If load==1, then 
+ * the in value is loaded into the memory location specified by address 
+ * (the loaded value will be emitted to out from the next time step onward).
+ */
+
+CHIP RAM4K {
+    IN in[16], load, address[12];
+    OUT out[16];
+
+    PARTS:
+    DMux8Way(in=load, sel=address[0..2], a=load1, b=load2, c=load3, d=load4, e=load5, f=load6, g=load7, h=load8);
+    RAM512(in=in, load=load1, address=address[3..11], out=outram1);
+    RAM512(in=in, load=load2, address=address[3..11], out=outram2);
+    RAM512(in=in, load=load3, address=address[3..11], out=outram3);
+    RAM512(in=in, load=load4, address=address[3..11], out=outram4);
+    RAM512(in=in, load=load5, address=address[3..11], out=outram5);
+    RAM512(in=in, load=load6, address=address[3..11], out=outram6);
+    RAM512(in=in, load=load7, address=address[3..11], out=outram7);
+    RAM512(in=in, load=load8, address=address[3..11], out=outram8);
+    Mux8Way16(a=outram1, b=outram2, c=outram3, d=outram4, e=outram5, f=outram6, g=outram7, h=outram8, sel=address[0..2], out=out);
+}

projects/03/einreichung/RAM512.hdl

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+// This file is part of the materials accompanying the book 
+// "The Elements of Computing Systems" by Nisan and Schocken, 
+// MIT Press. Book site: www.idc.ac.il/tecs
+// File name: projects/03/b/RAM512.hdl
+
+/**
+ * Memory of 512 registers, each 16 bit-wide. Out holds the value
+ * stored at the memory location specified by address. If load==1, then 
+ * the in value is loaded into the memory location specified by address 
+ * (the loaded value will be emitted to out from the next time step onward).
+ */
+
+CHIP RAM512 {
+    IN in[16], load, address[9];
+    OUT out[16];
+
+    PARTS:
+    DMux8Way(in=load, sel=address[0..2], a=load1, b=load2, c=load3, d=load4, e=load5, f=load6, g=load7, h=load8);
+    RAM64(in=in, load=load1, address=address[3..8], out=outram1);
+    RAM64(in=in, load=load2, address=address[3..8], out=outram2);
+    RAM64(in=in, load=load3, address=address[3..8], out=outram3);
+    RAM64(in=in, load=load4, address=address[3..8], out=outram4);
+    RAM64(in=in, load=load5, address=address[3..8], out=outram5);
+    RAM64(in=in, load=load6, address=address[3..8], out=outram6);
+    RAM64(in=in, load=load7, address=address[3..8], out=outram7);
+    RAM64(in=in, load=load8, address=address[3..8], out=outram8);
+    Mux8Way16(a=outram1, b=outram2, c=outram3, d=outram4, e=outram5, f=outram6, g=outram7, h=outram8, sel=address[0..2], out=out);
+}

projects/03/einreichung/RAM64.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/a/RAM64.hdl
+
+/**
+ * Memory of 64 registers, each 16 bit-wide. Out holds the value
+ * stored at the memory location specified by address. If load==1, then 
+ * the in value is loaded into the memory location specified by address 
+ * (the loaded value will be emitted to out from the next time step onward).
+ */
+
+CHIP RAM64 {
+    IN in[16], load, address[6];
+    OUT out[16];
+
+    PARTS:
+    DMux8Way(in=load, sel=address[0..2], a=load1, b=load2, c=load3, d=load4, e=load5, f=load6, g=load7, h=load8);
+    RAM8(in=in, load=load1, address=address[3..5], out=outram1);
+    RAM8(in=in, load=load2, address=address[3..5], out=outram2);
+    RAM8(in=in, load=load3, address=address[3..5], out=outram3);
+    RAM8(in=in, load=load4, address=address[3..5], out=outram4);
+    RAM8(in=in, load=load5, address=address[3..5], out=outram5);
+    RAM8(in=in, load=load6, address=address[3..5], out=outram6);
+    RAM8(in=in, load=load7, address=address[3..5], out=outram7);
+    RAM8(in=in, load=load8, address=address[3..5], out=outram8);
+    Mux8Way16(a=outram1, b=outram2, c=outram3, d=outram4, e=outram5, f=outram6, g=outram7, h=outram8, sel=address[0..2], out=out);
+}

projects/03/einreichung/RAM8.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/a/RAM8.hdl
+
+/**
+ * Memory of 8 registers, each 16 bit-wide. Out holds the value
+ * stored at the memory location specified by address. If load==1, then 
+ * the in value is loaded into the memory location specified by address 
+ * (the loaded value will be emitted to out from the next time step onward).
+ */
+
+CHIP RAM8 {
+    IN in[16], load, address[3];
+    OUT out[16];
+
+    PARTS:
+    DMux8Way(in=load, sel=address, a=load1, b=load2, c=load3, d=load4, e=load5, f=load6, g=load7, h=load8);
+    Register(in=in, load=load1, out=out1);
+    Register(in=in, load=load2, out=out2);
+    Register(in=in, load=load3, out=out3);
+    Register(in=in, load=load4, out=out4);
+    Register(in=in, load=load5, out=out5);
+    Register(in=in, load=load6, out=out6);
+    Register(in=in, load=load7, out=out7);
+    Register(in=in, load=load8, out=out8);
+    Mux8Way16(a=out1, b=out2, c=out3, d=out4, e=out5, f=out6, g=out7, h=out8, sel=address, out=out);
+}

projects/03/einreichung/Register.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/a/Register.hdl
+
+/**
+ * 16-bit register:
+ * If load[t] == 1 then out[t+1] = in[t]
+ * else out does not change
+ */
+
+CHIP Register {
+    IN in[16], load;
+    OUT out[16];
+
+    PARTS:
+    Bit(in=in[0], load=load, out=out[0]);
+    Bit(in=in[1], load=load, out=out[1]);
+    Bit(in=in[2], load=load, out=out[2]);
+    Bit(in=in[3], load=load, out=out[3]);
+    Bit(in=in[4], load=load, out=out[4]);
+    Bit(in=in[5], load=load, out=out[5]);
+    Bit(in=in[6], load=load, out=out[6]);
+    Bit(in=in[7], load=load, out=out[7]);
+    Bit(in=in[8], load=load, out=out[8]);
+    Bit(in=in[9], load=load, out=out[9]);
+    Bit(in=in[10], load=load, out=out[10]);
+    Bit(in=in[11], load=load, out=out[11]);
+    Bit(in=in[12], load=load, out=out[12]);
+    Bit(in=in[13], load=load, out=out[13]);
+    Bit(in=in[14], load=load, out=out[14]);
+    Bit(in=in[15], load=load, out=out[15]);
+}