diff --git a/projects/01/Hades/Not.hds b/projects/01/Hades/Not.hds
new file mode 100644
index 0000000..692a292
--- /dev/null
+++ b/projects/01/Hades/Not.hds
@@ -0,0 +1,14 @@
+# hades.models.Design file
+#  
+[name] unnamed
+[components]
+hades.models.io.LED i3 25800 9600 @N 1001 0
+hades.models.gates.Nand2 i2 21300 8400 @N 1001 1.0E-8
+hades.models.io.Ipin i1 20400 9600 @N 1001 U
+hades.models.io.Opin i0 25800 9600 @N 1001 5.0E-9
+[end components]
+[signals]
+hades.signals.SignalStdLogic1164 n1 3 i1 Y i2 A i2 B 3 2 20400 9600 21300 9600 2 21300 9000 21300 9600 2 21300 10200 21300 9600 1 21300 9600 
+hades.signals.SignalStdLogic1164 n0 2 i2 Y i3 A 1 2 25800 9600 24900 9600 0 
+[end signals]
+[end]
diff --git a/projects/01/Hades/hades_models_gates_Nand2.vhd b/projects/01/Hades/hades_models_gates_Nand2.vhd
new file mode 100644
index 0000000..c46a9e3
--- /dev/null
+++ b/projects/01/Hades/hades_models_gates_Nand2.vhd
@@ -0,0 +1,31 @@
+-- VHDL for hades.models.gates.Nand2: /unnamed/i2
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity hades_models_gates_Nand2 is 
+    port (
+         Y :       out  std_logic;
+         A :       in   std_logic;
+         B :       in   std_logic
+    );
+end hades_models_gates_Nand2;
+
+
+-- default architecture for: hades.models.gates.Nand2: /unnamed/i2
+--
+architecture SIMPLE of hades_models_gates_Nand2 is
+begin
+  Y <= not (A and B);
+end SIMPLE;
+
+
+
+configuration cfg_hades_models_gates_Nand2 of hades_models_gates_Nand2 is
+  for SIMPLE
+  end for;
+end cfg_hades_models_gates_Nand2;
+
+
diff --git a/projects/01/Hades/not.v b/projects/01/Hades/not.v
new file mode 100644
index 0000000..2b95626
--- /dev/null
+++ b/projects/01/Hades/not.v
@@ -0,0 +1,34 @@
+/**
+ * 16-bit Not gate: for i = 0..15: out[i] = Not in[i]
+ *
+ * Adapted from "The Elements of Computer Systems"
+ * by Nisan and Schocken, MIT Press.
+ *
+ * Adapted by Jeremiah Biard
+ * 7/19/2013
+ *
+ */
+ 
+module not16(
+  output [15:0] out,
+  input [15:0] in);
+  
+  not
+    n0(out[0], in[0]),
+    n1(out[1], in[1]),
+    n2(out[2], in[2]),
+    n3(out[3], in[3]),
+    n4(out[4], in[4]),
+    n5(out[5], in[5]),
+    n6(out[6], in[6]),
+    n7(out[7], in[7]),
+    n8(out[8], in[8]),
+    n9(out[9], in[9]),
+    n10(out[10], in[10]),
+    n11(out[11], in[11]),
+    n12(out[12], in[12]),
+    n13(out[13], in[13]),
+    n14(out[14], in[14]),
+    n15(out[15], in[15]);
+    
+endmodule
\ No newline at end of file