// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/b/RAM4K.hdl

/**
 * Memory of 4K registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM4K {
    IN in[16], load, address[12];
    OUT out[16];

    PARTS:
    DMux8Way(in=load, sel=address[0..2], a=load1, b=load2, c=load3, d=load4, e=load5, f=load6, g=load7, h=load8);
    RAM512(in=in, load=load1, address=address[3..11], out=outram1);
    RAM512(in=in, load=load2, address=address[3..11], out=outram2);
    RAM512(in=in, load=load3, address=address[3..11], out=outram3);
    RAM512(in=in, load=load4, address=address[3..11], out=outram4);
    RAM512(in=in, load=load5, address=address[3..11], out=outram5);
    RAM512(in=in, load=load6, address=address[3..11], out=outram6);
    RAM512(in=in, load=load7, address=address[3..11], out=outram7);
    RAM512(in=in, load=load8, address=address[3..11], out=outram8);
    Mux8Way16(a=outram1, b=outram2, c=outram3, d=outram4, e=outram5, f=outram6, g=outram7, h=outram8, sel=address[0..2], out=out);
}