// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/05/CPU.hdl

/**
 * The Hack CPU (Central Processing unit), consisting of an ALU,
 * two registers named A and D, and a program counter named PC.
 * The CPU is designed to fetch and execute instructions written in 
 * the Hack machine language. In particular, functions as follows:
 * Executes the inputted instruction according to the Hack machine 
 * language specification. The D and A in the language specification
 * refer to CPU-resident registers, while M refers to the external
 * memory location addressed by A, i.e. to Memory[A]. The inM input 
 * holds the value of this location. If the current instruction needs 
 * to write a value to M, the value is placed in outM, the address 
 * of the target location is placed in the addressM output, and the 
 * writeM control bit is asserted. (When writeM==0, any value may 
 * appear in outM). The outM and writeM outputs are combinational: 
 * they are affected instantaneously by the execution of the current 
 * instruction. The addressM and pc outputs are clocked: although they 
 * are affected by the execution of the current instruction, they commit 
 * to their new values only in the next time step. If reset==1 then the 
 * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather 
 * than to the address resulting from executing the current instruction. 
 */

CHIP CPU {

    IN  inM[16],         // M value input  (M = contents of RAM[A])
        instruction[16], // Instruction for execution
        reset;           // Signals whether to re-start the current
                         // program (reset==1) or continue executing
                         // the current program (reset==0).

    OUT outM[16],        // M value output
        writeM,          // Write to M? 
        addressM[15],    // Address in data memory (of M)
        pc[15];          // address of next instruction

    PARTS:
    // Put your code here:
	
	
	//Controlbus
	// A/C-Instruction and Controlbus
	Not(in=instruction[15],out=on);
	//d1
	Or(a=on,b=instruction[5],out=loadA);
	And(a=instruction[15],b=instruction[12],out=AoderMem);
	//d2
	And(a=instruction[15],b=instruction[4],out=loadD);
	//d3 -- writeM
	And(a=instruction[15],b=instruction[3],out=writeM);
	//j3
	And(a=instruction[15],b=instruction[0],out=j3);
	//j2
	And(a=instruction[15],b=instruction[1],out=j2);
	//j1
	And(a=instruction[15],b=instruction[2],out=j1);
	Not(in=zr,out=notzr);
	Not(in=ng,out=notng);
	And(a=notzr,b=notng,out=notzrAndNoting);
	And(a=notzrAndNoting,b=j3,out=jg3);
	
	And(a=zr,b=j2,out=jg2);
	And(a=ng,b=j1,out=jg1);	
	Or(a=jg3,b=jg2,out=jg23);
	Or(a=jg23,b=jg1,out=loadPC);
	
	// Hier addressM[15]-Ausgang der CPU
	ARegister(in=mux1,load=loadA,out=outAReg,out[0..14]=addressM);
	
	//M1
	Mux16(a=outM2,b=instruction,sel=on,out=mux1);
	//M2
	Mux16(a=outAReg,b=inM,sel=AoderMem,out=AM);
 
	DRegister(in=outM2,load=loadD,out=outD);
	
	// Das out könnte nicht funktionieren, d.h. die Verteilung zum D-Register und zum Mux
	
	ALU(x=outD,y=AM,zx=instruction[11],nx=instruction[10],zy=instruction[9],ny=instruction[8],f=instruction[7],no=instruction[6],zr=zr,ng=ng,out=outM,out=outM2);
	
	//Counter
	PC(in=outAReg,load=loadPC, inc=true,reset=reset,out[0..14]=pc);
 
 }