41 lines
818 B
VHDL
41 lines
818 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity AND_GATE is
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Port ( A : in STD_LOGIC;
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B : in STD_LOGIC;
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O : out STD_LOGIC);
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end NAND_GATE;
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entity and_nor_top is
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Port ( IN1 : in STD_LOGIC;
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IN2 : in STD_LOGIC;
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IN3 : in STD_LOGIC;
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IN4 : in STD_LOGIC;
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OUT1 : out STD_LOGIC;
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OUT2 : out STD_LOGIC);
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end nand_nor_top;
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architecture Behavioral of nand_nor_top is
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signal A1 : STD_LOGIC;
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signal A2 : STD_LOGIC;
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signal X1 : STD_LOGIC;
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signal B1 : STD_LOGIC;
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signal B2 : STD_LOGIC;
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signal Y1 : STD_LOGIC;
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begin
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X1 <= A1 nand A2;
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Y1 <= B1 nor B2;
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-- compensation for inverting inputs and outputs
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A1 <= not IN1;
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A2 <= not IN2;
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OUT1 <= not X1;
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B1 <= not IN3;
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B2 <= not IN4;
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OUT2 <= not Y1;
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end Behavioral; |