12 lines
207 B
VHDL
12 lines
207 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity notGate is
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port (a, b : in std_logic;
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out : out std_logic);
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end notGate;
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architecture hardware of notGate is
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begin
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out <= a nand a;
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end hardware; |