14 lines
250 B
VHDL
14 lines
250 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity NAND_GATE is
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Port ( A : in STD_LOGIC;
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B : in STD_LOGIC;
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O : out STD_LOGIC);
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end NAND_GATE;
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architecture Behavioral of NAND_GATE is
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begin
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O <= not (A and B);
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end Behavioral;
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