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Elemente/And.tex

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+\begin{multicols}{2}
+[
+\section{AND}
+]
+
+\subsection{VHDL}
+ \begin{minted}{vhdl}
+/**
+ * And gate: 
+ * out = 1 if (a == 1 and b == 1)
+ *       0 otherwise
+ */
+
+CHIP And {
+    IN a, b;
+    OUT out;
+
+    PARTS:
+        Nand(a=a ,b=b ,out=nandout);
+        Not(in=nandout ,out=out);
+}
+\end{minted}
+
+\subsection{Wertetabelle}
+\begin{table}[H]
+    \centering
+    \begin{tabular}{cc|c}
+         a&  b& a $\wedge$ b\\ \hline
+         0&  0& 0\\
+         0&  1& 0\\
+         1&  0& 0\\
+         1&  1& 1\\
+    \end{tabular}
+    \label{tab:and}
+\end{table}
+
+\subsection{Aufbau mit Nand}
+\begin{figure}[H]
+\centering
+    \centering
+    \input{Grafiken/AndANSI}
+    \caption{Enter Caption}
+    \label{fig:enter-label}
+\end{figure}
+
+
+\subsection{Darstellung nach IEC}
+\begin{figure}[H]
+\centering
+    \centering
+    \includegraphics[width=0.75\linewidth]{IEC/AndIEC.png}
+    \caption{Enter Caption}
+    \label{fig:enter-label}
+\end{figure}
+
+
+\end{multicols}
+
+
+

Elemente/Not.tex

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+\section{Not}
+
+\begin{minipage}[t]{0.5\linewidth} 
+    \begin{minted}{vhdl}
+/**
+ * Not gate:
+ * out = not in
+ */
+
+CHIP Not {
+    IN in;
+    OUT out;
+
+    PARTS:
+    Nand(a=in,b=in,out=out);
+    // Put your code here:
+}
+\end{minted}
+    \end{minipage}\hfill
+%\raisebox{\dimexpr \ht\strutbox-\totalheight}{
+\raisebox{-0.5\height}{
+\begin{minipage}[t]{0.4\linewidth} 
+    \begin{figure}[H]
+\centering
+\include{Grafiken/NotANSI}\caption{Not(ANSI)}
+\label{fig:NotANSI}
+\end{figure}
+\end{minipage}}
+
+%%%%%%%%%%%%%%%%%%
+
+\begin{minipage}[t]{0.5\linewidth} 
+\begin{table}[H]
+    \centering
+    \begin{tabular}{c|c}
+         in&  $\neg$ in\\ \hline
+         0&   1\\
+         1&   0\\
+\end{tabular}
+\label{tab:not}
+\end{table}
+\end{minipage}\hfill
+\raisebox{-0.5\height}{
+\begin{minipage}[t]{0.4\linewidth} 
+\begin{figure}[H]
+\centering
+\includegraphics{IEC/NotIEC.pdf}\caption{Not(IEC)}
+\label{fig:NotIEC}
+\end{figure}
+
+\end{minipage}}
+
+\begin{figure}
+    \centering
+    \includegraphics[width=0.25\linewidth]{Grafiken/NotTransistor.png}
+    \caption{Enter Caption}
+    \label{fig:enter-label}
+\end{figure}
+%%%%%%%%%%%%%%%%%%
+

Elemente/Or.tex

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+\begin{multicols*}{2}
+[
+\section{OR}
+]
+
+\subsection{VHDL}
+\begin{minted}{vhdl}
+ /**
+ * Or gate:
+ * out = 1 if (a == 1 or b == 1)
+ *       0 otherwise
+ */
+
+CHIP Or {
+    IN a, b;
+    OUT out;
+
+    PARTS:
+    Not(in=a,out=nota);
+    Not(in=b,out=notb);
+    Nand(a=nota,b=notb,out=out);
+}
+\end{minted}
+
+\subsection{Wertetabelle}
+\begin{table}[H]
+    \centering
+    \begin{tabular}{cc|c}
+         a&  b& out\\ \hline
+         0&  0& 0\\
+         0&  1& 1\\
+         1&  0& 1\\
+         1&  1& 1\\
+    \end{tabular}
+    \label{tab:or}
+\end{table}
+
+\subsection{Aufbau mit Nand}
+\begin{figure}[H]
+\centering
+    \centering
+    \include{Grafiken/OrANSIComplete}
+    \caption{Enter Caption}
+    \label{fig:enter-label}
+\end{figure}
+
+\subsection{Darstellung nach ANSI}
+\begin{figure}[H]
+\centering
+    \centering
+    \include{Grafiken/OrANSI}
+    \caption{Enter Caption}
+    \label{fig:enter-label}
+\end{figure}
+
+\subsection{Darstellung nach IEC}
+\begin{figure}[H]
+\centering
+    \centering
+    \includegraphics[width=0.75\linewidth]{IEC/OrIEC.png}
+    \caption{Enter Caption}
+    \label{fig:enter-label}
+\end{figure}
+
+
+\end{multicols*}
+

Elemente/XOR.tex

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+%\begin{multicols*}{2}
+%[
+\section{XOR}
+%]
+
+\subsection{VHDL}
+\begin{minted}{vhdl}
+
+/**
+ * Exclusive-or gate:
+ * out = not (a == b)
+ */
+
+CHIP Xor {
+    IN a, b;
+    OUT out;
+
+    PARTS:
+    Not(in=a, out=nota);
+    Not(in=b, out=notb);    
+    Nand(a=nota, b=b, out=nandout1);
+    Nand(a=a, b=notb, out=nandout2);
+    Nand(a=nandout1, b=nandout2, out=out);
+}
+ 
+\end{minted}
+
+\subsection{Wertetabelle}
+\begin{table}[H]
+    \centering
+    \begin{tabular}{cc|c}
+         a&  b& $a\oplus b = out$ \\ \hline
+         0&  0& 0\\
+         0&  1& 1\\
+         1&  0& 1\\
+         1&  1& 0\\
+    \end{tabular}
+    \label{tab:or}
+\end{table}
+
+\subsection{Aufbau mit Nand}
+\begin{figure}[H]
+\centering
+    \centering
+    \include{Grafiken/XORANSI}
+    \caption{Enter Caption}
+    \label{fig:enter-label}
+\end{figure}
+
+
+
+\begin{table}
+    \centering
+    \begin{tabular}{|c|c|c|c|c|c|} \hline 
+         a&  b&  N1&  N2&  $N1\barwedge b  = N3$&$N2\barwedge a=N4$\\ \hline 
+         0&  0&  1&  1&  1 &1\\ \hline 
+         0&  1&  1&  0&  0&0\\ \hline 
+         1&  0&  0&  1&  1 &1\\ \hline 
+         1&  1&  0&  0&  1&1\\ \hline
+\begin{tikzpicture} \draw[color=green,line width=3] (0,0) --(0.3,0);
+\end{tikzpicture} & \begin{tikzpicture}
+\draw[color=red,line width=3] (0,0)--(0.3,0);
+\end{tikzpicture} & \begin{tikzpicture}
+\draw[color=red,line width=3] (0,0)--(0.3,0);
+\end{tikzpicture} & \begin{tikzpicture}\draw[color=green,line width=3] (0,0) --(0.3,0);
+\end{tikzpicture}  &\begin{tikzpicture}
+\draw[color=red,line width=3] (0,0)--(0.3,0);
+\end{tikzpicture} &\begin{tikzpicture}
+\draw[color=green,line width=3] (0,0)--(0.3,0);
+\end{tikzpicture}\\\hline
+    \end{tabular}
+    \caption{Caption}
+    \label{tab:my_label}
+\end{table}
+
+
+\subsection{Darstellung nach ANSI}
+\begin{figure}[H]
+\centering
+    \centering
+ %   \include{Grafiken/OrANSI}
+    \caption{Enter Caption}
+    \label{fig:enter-label}
+\end{figure}
+
+\subsection{Darstellung nach IEC}
+\begin{figure}[H]
+\centering
+    \centering
+%    \includegraphics[width=0.75\linewidth]{IEC/OrIEC.png}
+    \caption{Enter Caption}
+    \label{fig:enter-label}
+\end{figure}
+
+
+%\end{multicols*}
+