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Sven Riwoldt
2024-04-06 18:15:41 +02:00
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%\begin{multicols*}{2}
%[
\section{XOR}
%]
\subsection{VHDL}
\begin{minted}{vhdl}
/**
* Exclusive-or gate:
* out = not (a == b)
*/
CHIP Xor {
IN a, b;
OUT out;
PARTS:
Not(in=a, out=nota);
Not(in=b, out=notb);
Nand(a=nota, b=b, out=nandout1);
Nand(a=a, b=notb, out=nandout2);
Nand(a=nandout1, b=nandout2, out=out);
}
\end{minted}
\subsection{Wertetabelle}
\begin{table}[H]
\centering
\begin{tabular}{cc|c}
a& b& $a\oplus b = out$ \\ \hline
0& 0& 0\\
0& 1& 1\\
1& 0& 1\\
1& 1& 0\\
\end{tabular}
\label{tab:or}
\end{table}
\subsection{Aufbau mit Nand}
\begin{figure}[H]
\centering
\centering
\include{Grafiken/XORANSI}
\caption{Enter Caption}
\label{fig:enter-label}
\end{figure}
\begin{table}
\centering
\begin{tabular}{|c|c|c|c|c|c|} \hline
a& b& N1& N2& $N1\barwedge b = N3$&$N2\barwedge a=N4$\\ \hline
0& 0& 1& 1& 1 &1\\ \hline
0& 1& 1& 0& 0&0\\ \hline
1& 0& 0& 1& 1 &1\\ \hline
1& 1& 0& 0& 1&1\\ \hline
\begin{tikzpicture} \draw[color=green,line width=3] (0,0) --(0.3,0);
\end{tikzpicture} & \begin{tikzpicture}
\draw[color=red,line width=3] (0,0)--(0.3,0);
\end{tikzpicture} & \begin{tikzpicture}
\draw[color=red,line width=3] (0,0)--(0.3,0);
\end{tikzpicture} & \begin{tikzpicture}\draw[color=green,line width=3] (0,0) --(0.3,0);
\end{tikzpicture} &\begin{tikzpicture}
\draw[color=red,line width=3] (0,0)--(0.3,0);
\end{tikzpicture} &\begin{tikzpicture}
\draw[color=green,line width=3] (0,0)--(0.3,0);
\end{tikzpicture}\\\hline
\end{tabular}
\caption{Caption}
\label{tab:my_label}
\end{table}
\subsection{Darstellung nach ANSI}
\begin{figure}[H]
\centering
\centering
% \include{Grafiken/OrANSI}
\caption{Enter Caption}
\label{fig:enter-label}
\end{figure}
\subsection{Darstellung nach IEC}
\begin{figure}[H]
\centering
\centering
% \includegraphics[width=0.75\linewidth]{IEC/OrIEC.png}
\caption{Enter Caption}
\label{fig:enter-label}
\end{figure}
%\end{multicols*}