61 lines
947 B
TeX
61 lines
947 B
TeX
\begin{multicols}{2}
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[
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\section{AND}
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]
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\subsection{VHDL}
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\begin{minted}{vhdl}
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/**
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* And gate:
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* out = 1 if (a == 1 and b == 1)
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* 0 otherwise
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*/
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CHIP And {
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IN a, b;
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OUT out;
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PARTS:
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Nand(a=a ,b=b ,out=nandout);
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Not(in=nandout ,out=out);
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}
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\end{minted}
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\subsection{Wertetabelle}
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\begin{table}[H]
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\centering
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\begin{tabular}{cc|c}
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a& b& a $\wedge$ b\\ \hline
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0& 0& 0\\
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0& 1& 0\\
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1& 0& 0\\
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1& 1& 1\\
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\end{tabular}
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\label{tab:and}
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\end{table}
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\subsection{Aufbau mit Nand}
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\begin{figure}[H]
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\centering
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\centering
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\input{Grafiken/AndANSI}
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\caption{Enter Caption}
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\label{fig:enter-label}
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\end{figure}
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\subsection{Darstellung nach IEC}
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\begin{figure}[H]
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\centering
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\centering
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\includegraphics[width=0.75\linewidth]{IEC/AndIEC.png}
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\caption{Enter Caption}
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\label{fig:enter-label}
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\end{figure}
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\end{multicols}
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