Projekt 5 beendet, ein Krampf

This commit is contained in:
Sven Riwoldt
2023-08-06 10:44:10 +02:00
parent 1cb42461db
commit 3ad3d596b0
3 changed files with 74 additions and 44 deletions

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@@ -45,21 +45,44 @@ CHIP CPU {
//Controlbus //Controlbus
// A/C-Instruction and Controlbus // A/C-Instruction and Controlbus
Not(in=instruction[15],out=on); Not(in=instruction[15],out=on);
OR(a=on,b=instruction[5],out=); //d1
AND(a=instruction[15],b=instruction[12],out=); Or(a=on,b=instruction[5],out=loadA);
AND(a=instruction[15],b=instruction[4],out=); And(a=instruction[15],b=instruction[12],out=AoderMem);
AND(a=instruction[15],b=instruction[3],out=); //d2
AND(a=instruction[15],b=instruction[0],out=); And(a=instruction[15],b=instruction[4],out=loadD);
AND(a=instruction[15],b=instruction[1],out=); //d3 -- writeM
AND(a=instruction[15],b=instruction[2],out=); And(a=instruction[15],b=instruction[3],out=writeM);
//j3
And(a=instruction[15],b=instruction[0],out=j3);
//j2
And(a=instruction[15],b=instruction[1],out=j2);
//j1
And(a=instruction[15],b=instruction[2],out=j1);
Not(in=zr,out=notzr); Not(in=zr,out=notzr);
Not(in=ng,out=notng); Not(in=ng,out=notng);
AND(a=notzr,b=notng,out=); And(a=notzr,b=notng,out=notzrAndNoting);
AND(a=,b=,out=); And(a=notzrAndNoting,b=j3,out=jg3);
AND(a=,b=,out=);
AND(a=,b=,out=);
OR(a=,b=,out=);
OR(a=,b=,out=);
Mux16(a=outM,b=instruction,sel=on,out=) And(a=zr,b=j2,out=jg2);
} And(a=ng,b=j1,out=jg1);
Or(a=jg3,b=jg2,out=jg23);
Or(a=jg23,b=jg1,out=loadPC);
// Hier addressM[15]-Ausgang der CPU
ARegister(in=mux1,load=loadA,out=outAReg,out[0..14]=addressM);
//M1
Mux16(a=outM2,b=instruction,sel=on,out=mux1);
//M2
Mux16(a=outAReg,b=inM,sel=AoderMem,out=AM);
DRegister(in=outM2,load=loadD,out=outD);
// Das out könnte nicht funktionieren, d.h. die Verteilung zum D-Register und zum Mux
ALU(x=outD,y=AM,zx=instruction[11],nx=instruction[10],zy=instruction[9],ny=instruction[8],f=instruction[7],no=instruction[6],zr=zr,ng=ng,out=outM,out=outM2);
//Counter
PC(in=outAReg,load=loadPC, inc=true,reset=reset,out[0..14]=pc);
}

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@@ -19,5 +19,7 @@ CHIP Computer {
IN reset; IN reset;
PARTS: PARTS:
// Put your code here: CPU(inM=inmm, instruction=ins, reset=reset, outM=outtm, writeM=wm, addressM=am, pc=pco);
Memory(in=outtm, load=wm, address=am, out=inmm);
ROM32K(address=pco, out=ins);
} }

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@@ -27,5 +27,10 @@ CHIP Memory {
OUT out[16]; OUT out[16];
PARTS: PARTS:
// Put your code here: DMux4Way(in=load,sel=address[13..14],a=ram1,b=ram2,c=loadscreen,d=loadkeyboard);
Or(a=ram1, b=ram2, out=ramload);
RAM16K(in=in, load=ramload, address=address[0..13], out=outram);
Screen(in=in, load=loadscreen, address=address[0..12], out=outscreen);
Keyboard(out=outkeyb);
Mux4Way16(a=outram, b=outram, c=outscreen, d=outkeyb, sel=address[13..14], out=out);
} }